1. Field of the Invention
The present invention relates to a semiconductor device, in particular, a semiconductor device having a three-dimensional structure MISFET (hereinafter, referred to a “three-dimensional FET”).
2. Description of Related Art
As a method of reducing the size of the MISFET (to achieve effects such as a suppression of short channel effect), the so-called three-dimensional FET is used for improving channel charge control capability of the gate electrode in place of a typical planar MISFET. The three-dimensional FET is a type of SOI (silicon on insulator) devices. The fin MISFET (FinFET) and the double gate FET (DG-FET) are typical three-dimensional FETs.
As an example of the three-dimensional FET, an SRAM (static random access memory) formed of a FinFET is disclosed in the following document: Zheng Guo et al., “FinFET-Based SRAM Design”, International Symposium on Low Power Electronics and Design, pp. 2-7, 2005 (ISLPED '05). In this technique, by adopting the FinFET as an FET of the SRAM, an SRAM with small cell size can be realized.
With regard to devices including the three-dimensional FET including the Fin FET or the planar SOI, the heat generation often becomes troublesome. For improving the heat dissipation of such devices, various techniques has been investigated. However, most of such investigations are directed to the planar SOI device, and the three-dimensional FET has not been sufficiently considered. The heat dissipation of the three-dimensional FET must be considered from different viewpoints from the planar SOI device, since their structures are different to each other. Particularly, in the planar SOI device, the device isolation is performed by partially oxidizing a semiconductor layer (SOI layer) formed on the whole surface of a wafer, while, in the three-dimensional FET, the device isolation is performed by forming semiconductor layers separately on an insulating film. Generally, the heat dissipation is more important technical issue for the three-dimensional FET than the planar SOI device.
More specifically, Japanese Laid-Open Patent Application JP-P2004-72017A discloses a technique for using metal interconnections on an upper layer of the planar SOI device as a heat dissipator. Japanese Laid-Open Patent Application JP-P2004-363136A discloses a structure of the planar SOI device in which a gate electrode of MOSFET used as an ESD protection element is shaped as a ring and a source region is separated from the outside of a source region with a shield plate electrode. With such structure, since the SOI layer forms continuous area, the heat dissipation efficiency is improved. In Japanese Laid-Open Patent Application JP-P2005-197462A, even the heat dissipation problem is not described, a structure in which a gate electrode and a channel region (referred to as a “well” in this document) become shorted is disclosed. With the structure disclosed in this document, a well of a P-type FET is joined with a well of an N-type FET by p-n junction.
Japanese Laid-Open Patent Application JP-P2006-19578A discloses the heat dissipation of the FinFET. This document discloses a structure in which a gate electrode and a channel region are shorted to reduce power consumption of a FinFET and suppress short channel effect. With this structure, the heat generated in a source and a drain is dissipated through a gate electrode.
Japanese Laid-Open Patent Application JP-P2005-116969A discloses an inverter circuit chain, which is one of the techniques of a logic circuit formed by using the three-dimensional FET. FIG. 1 in this document shows a layout diagram of the inverter circuit chain. In this figure, sources of an inverter circuit (104, 105) are not coupled to each other by a semiconductor layer (there is no common semiconductor layer) but are electrically connected to each other with a metal interconnection (106, 107 are source electrode interconnections). Generally, when the three-dimensional FET forms a functional circuit obtained by combining logic gate circuits, sources of FET each forming the logic gate circuit are connected to each other with a metal interconnection as this document JP-P2005-116969A. Accordingly, with such structure, since the heat from the metal interconnection is dissipated from a semiconductor layer through a contact plug, the amount of dissipated heat is limited by the thermal resistance of the contact plug. As a result, heat exhaustion of the semiconductor layer is limited by the thermal resistance of the contact plug.